Tutorial Speakers

Monday, November 7

TUTORIAL-1 9:00-10:30
Design of PLLs with Binary Phase Detectors for Frequency Synthesis & CDR

Dr.Asad Abidi

Asad Abidi
University of California, Los Angeles

Biography

Asad Abidi received the MS and PhD degrees in EE from the University of California, Berkeley.
After working at Bell Laboratories, Murray Hill, NJ, he joined the EE faculty at UCLA, where he is Distinguished Chancellor's Professor. He and his students have contributed fundamental circuit analysis and design to RF-CMOS.
Asad Abidi has received the IEEE Donald O. Pederson Award in Solid-State Circuits and the Best Paper Award from the IEEE Journal of Solid-State Circuits. He is IEEE Fellow, member of the US National Academy of Engineering, and fellow of TWAS, the world academy of sciences.

Abstract

Wherever there is an oscillator, there is a PLL. As the design of PLLs has progressed from all-analog to all-digital, circuit designers increasingly resort to complex simulations that limits exploration of the design space.
We will show analytical methods that enable fast and accurate design of PLLs with strong nonlinearity, that is, one-bit elements in the phase detector. This can greatly simplify design effort, and allow use of analog or digital loop filters.
The analysis will be applied to various PLLs taken from the literature, and it will show how close those designs are to optimal for the targets.

TUTORIAL-2 10:50-12:20
Accelerating Deep Convolutional Neural Networks Using Specialized Hardware in the Datacenter

Dr.Joo-Young Kim

Joo-Young Kim
Microsoft Research

Biography

Joo-Young Kim received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST) in 2005, 2007, and 2010, respectively, and joined Microsoft Research in 2012.
He is currently a Senior Research Hardware Design Engineer in Microsoft Research NExT. His research focuses on design of energy efficient hardware architectures for high valued applications such as machine learning, data compression, and image processing. He is a member of the Catapult project at Microsoft, which was the first attempt to use a fabric of FPGAs at scale to accelerate cloud services in datacenter.

Abstract

Recent breakthroughs in the development of multi-layer convolutional neural networks have led to state-of-the-art improvements in the accuracy of non-trivial recognition tasks such as large-category image classification and automatic speech recognition. These many-layered neural networks are large, complex, and require substantial computing resources to train and evaluate. Unfortunately, these demands come at an inopportune moment due to the recent slowing of gains in commodity processor performance.
Hardware specialization in the form of GPGPUs, FPGAs, and ASIC offers a promising path towards major leaps in processing capability while achieving high energy efficiency. At Microsoft, an effort is underway to accelerate Deep Convolutional Neural Networks (CNN) using servers in the datacenter augmented with FPGAs. Initial efforts to implement a single-node CNN accelerator on a mid-range FPGA show significant promise, resulting in respectable performance relative to prior FPGA designs, multithreaded CPU implementations and high-end GPGPUs, at a fraction of the power. In the future, combining multiple FPGAs over a low-latency communication fabric offers further opportunity to train and evaluate models of unprecedented size and quality.

TUTORIAL-3 13:40-15:10
Wireless systems from link budget to RFIC

Dr.Aarno Pärssinen

Aarno Pärssinen
University of Oulu

Biography

Aarno Pärssinen received the M.Sc. and D.Sc. degrees in EE from Helsinki University of Technology, Finland, in 1995, and 2000, respectively. In 1996, he was a Research Visitor at the University of California at Santa Barbara. From 2000 to 2011 he was with Nokia Research Center, Helsinki, Finland. From 2011 to 2013, he was at Renesas Mobile Corporation, Helsinki, Finland. In 2013 he joined Broadcom, Helsinki, Finland as part of business acquisition until September 2014. Since September 2014 he has been with University of Oulu, Centre for Wireless Communications, Oulu, Finland where he is currently a Professor. His research interests include wireless systems and transceiver architectures for wireless communications with special emphasis on the RF and analog integrated circuit and system design. He has authored and co-authored one book, one chapter of a book, more than 50 international journal and conference papers and holds several patents. Since 2007, he has been serving as a ITPC member of ISSCC and he is currently the chair of the wireless subcommittee.

Abstract

RF transceivers cover wide span of applications from high speed data in wide and local area networks to extremely low power radios for IoE. Requirements and specifications for RFIC implementations need to be defined from system or application targets and they depend on data rate and range requirements as well as other radios in the vicinity. RF system design is based on link budget and radio interference environment. Those determine key parameters like sensitivity and selectivity for receivers and output power and spectrum mask for transmitters
This tutorial introduces various aspects from system concepts to RFIC performance requirements. Examples of RFIC's for different wireless systems will be presented highlighting how performance requirements can be met. Finally, key trends towards 5G cellular systems will be introduced with focus on RF transceiver challenges.

TUTORIAL-4 15:30-17:00
Circuit Techniques for Serial Data Communications

Dr.Hirotaka Tamura

Hirotaka Tamura
Fujitsu Laboratories LTD.

Biography

Hirotaka Tamura received his B.S., M.S., and Ph.D. degrees in electronic engineering from Tokyo University, Tokyo, Japan, in 1977, 1979, and 1982. He joined Fujitsu Laboratories in 1982. After being involved in the development of different exploratory devices such as Josephson junction devices and high-temperature superconductor devices, he moved into the field of CMOS high-speed signaling in 1996 and got involved in the development of a multi-channel high-speed I/O for server interconnects. Since then, he has been working in the area of architecture- and transistor-level design for CMOS high-speed signaling circuits. Since 2014, he has been expanding his area of expertise to cover devices, circuits, and architectures for post-Moore-era computing. He is a Fellow of the IEEE.

Abstract

Information Technology (IT), which plays significant roles in our everyday life, utilizes different means of computing and communicating to store, retrieve, transfer, and process data. Due to physical and cost requirements, these basic data-handling functions of IT are performed by different physical entities, i.e., storing and retrieving by memories, processing by processors, and transferring by various communication devices.
Among the basic functions of IT, this tutorial deals with data transfer through physical layers, focusing on circuit techniques for data transfer through wireline communication channels. The tutorial covers the basics of wireline communications and CMOS-circuit techniques used for electric signal transfer through metallic channels. The advanced topics I will talk about are an electrical 56-Gb/s NRZ transceiver and packaging techniques for Si-photonics devices.