Plenary Speakers
Tuesday, November 10
Plenary Talk I 9:20-10:05
Digital Innovation and AI semiconductor in the AI and Post-Corona era
Kiyoung Choi, PhD
Minister, Ministry of Science and ICT, Republic of Korea
Abstract
The world is facing enormous changes caused by disruptive digital technologies such as Artificial Intelligence and big data. In particular, the significant changes of economic and social structures such as accelerated digital transformation and growth of contactless industries due to COVID-19 are actually opportunities to reconfirm the importance of digital capabilities. In this speech, I would like to present the direction of national digital innovation in the era of artificial intelligence and post-corona, based on the 'AI National Strategy' and 'Digital New Deal' policies being pursued by the Korean government.
In addition, I will discuss the importance of AI semiconductor, which is a key foundation that determines the competitiveness of AI and data ecosystems, and is growing as a new semiconductor paradigm in the AI era. Also, I will share with participants about Korea's new challenges to foster AI semiconductors.
Biography
Since September 2019, Kiyoung Choi has been serving as the Minister of Science and ICT, which is in charge of formulating policies in the 4th Industrial Revolution as well as the fields of science and ICT.
Prior to his current position, Mr. Choi was professor of the Department of Electrical and Computer Engineering, Seoul National University from 1991 to 2019. During that time, he served as Chief Vice President of the Institute of Semiconductors Engineers and as Director of Neural Processing Research Center and Embedded Systems Research Center at Seoul National University. From 1989 to 1991, he was with Cadence Design Systems, Inc., USA.
Mr. Choi received the Ph.D. degree in electrical engineering from Stanford University, USA, in 1989, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology in 1980, and the B.S. degree in electronics engineering from Seoul National University in 1978.
Plenary Talk II 10:05-10:50
Intelligent Chips and Technologies for AIoT Era
Yu-Chin Hsu, PhD
Chairman, BigObject, Inc.
Abstract
The re-emergence of AI in 2016 has greatly influenced the needs for computing. It is estimated the amount of computing used in the largest AI training runs grew more than 300,000x from 2012 to 2018. Roughly, it doubles every 3.5 months. Semiconductor industry will continue to be important in the new era. Foreseeing the coming of AI and data age, in Taiwan we initiated several major programs in AI in 2017. For AI edge computing, we focus on six major areas: (1) advanced sensors, circuits and systems. (2) next generation memory design. (3) neuromorphic computing and AI chip. (4) security for Internet of thing. (5) UAV components, circuits and systems. (6) advanced semiconductor process, material, and components. In this presentation, we review the overall plan for the AI edge computing program, and present some of the results that has been published. We anticipate the industry will be benefit from the talents being cultivated and the results to be applied in industrial applications.
Biography
Dr. Hsu has more than 30 years of experience in the EDA. He found NexSyn Inc. which was merged into Avant! in 1995, and co-found Novas Inc. (part of SpringSoft) in 1999, and was merged into Synopsys in 2012. He served in senior management roles in Avant!, SpringSoft, and Synopsys.
He held faculty position in Tsing-Hua University, Taiwan, and University of California, Riverside, USA.
Dr. Hsu was appointed as Debuty Minister of Ministry of Science and Technology, Taiwan, from 2017.04-2020.05. During his tenure, he helped initiating the artificial intelligence(AI) strategic programs and semiconductor for AI programs in Taiwan. He also managed the academia-industrial collaboration programs, Science Park, and entrepreneurship and innovation ecosystem.
Dr. Hsu holds a B.S. from the National Taiwan University, and an M.S. and a Ph.D. from the University of Illinois Urbana-Champaign.
Wednesday, November 11
Plenary Talk III 8:30-9:15
Co-optimization targeting future interconnection
Wei Tsao, PhD
Chief Architect & Shanghai Branch Director of Analog Design Department, Hisilicon
Abstract
The future interconnection techniques should satisfy greater bandwidth, less latency, and higher energy efficiency for both out-of-chip and inside-chip scenarios; while the engineering constraints and cost-performance trade-off on channel characteristics, modulation/coding technique, and analog-digital transceiver scheme, must restrict the fulfilment of interconnection design target. In order to attain the destination mentioned above, co-optimization is employed toward channel, modulation/coding, and transceiver scheme. In this paper, the requirement for future interconnection, channel situation, and some implementation trends are presented.
Biography
Dr. Wei Tsao is currently Chief Architect and Shanghai Branch Director of Analog Design Department, Hisilicon Inc., responsible for architecture competitiveness of Hisilicon analog-digital mixed IP, and in charge of analog development team in Shanghai. He joined in Hisilicon in 2009, and has delivered many key analog-digital mixed IP for Huawei products, including the Ethernet PHY, High Bandwidth Memory interface PHY, Ultra-high speed converters, PCIE SerDes etc. Before joining Hisilicon, Dr. Wei Tsao has mixed signal chip development and management experiences in high-speed interconnect PHY/SerDes area for storage and communication products, with several companies in US. He has worked as architect in mixed signal area for 20 years.
Dr. Wei Tsao has published more than 10 papers in journals and conferences, he has many China and US patents as first or co-inventor. His current main interest is in Ultra-high speed physical layer technique, mixed signal system architecture and automotive mixed signal chip solution. Dr. Wei Tsao received his BS and PhD from Shanghai Jiaotong University.
Plenary Talk IV 9:15-10:00
Supercomputer Fugaku - Co-designed with application developers/researchers -
Mr. Toshiyuki Shimizu
Senior Director, Platform Development Unit, Fujitsu Limited
Abstract
Supercomputer FUGAKU has been developed through co-design efforts with application developers/researchers and system-software/hardware designers. The design targets of Fugaku were high application execution efficiency, low-power consumption, and ease of use. In this paper, the Fugaku architecture and evaluation results are briefly explained.
Performance estimations of target applications in the design phase and using real hardware are compared.
Biography
Mr. Toshiyuki Shimizu is Senior Director, Platform Development Unit, at Fujitsu Limited. Mr. Shimizu has been deeply and continuously involved in the development of scalar parallel supercomputers, large SMP enterprise servers, and x86 cluster systems. His primary research interest is in interconnect architecture, most recently culminating in the development of the Tofu interconnect for the K computer and PRIMEHPC series.
He leads the development of Fujitsu’s high-end supercomputer PRIMEHPC series and the Fugaku supercomputer formerly known as Post-K. Mr. Shimizu received his Masters of Computer Science degree from Tokyo Institute of Technology in 1988.